1. Field of the Invention
Embodiments of the invention relate to a semiconductor memory device and a related method. In particular, embodiments of the invention relate to a semiconductor memory device comprising a data path controller and a related method.
This application claims priority to Korean Patent Application 10-2006-0079424, filed on Aug. 22, 2006, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
The accuracy, speed, and corresponding bandwidth of data transmissions between contemporary central processing units (CPUs) and associated semiconductor memory devices are increasingly important to the proper operation of incorporating products.
In this regard, there are several types of Dynamic Random Access Memory (DRAM) devices commonly used with CPUs. One type is the single data rate (SDR) DRAM. A SDR DRAM accesses data in response to the rising edge of a controlling clock signal. Another type is the double data rate (DDR) DRAM. A DDR DRAM accesses data on both the rising and falling edges of a controlling clock signal, and generally provides greater data bandwidth over SDR DRAMs. Quadri-Data Rate (QDR) DRAMs have recently been introduced.
FIG. (FIG.) 1 is a timing diagram illustrating read and write operations for a SDR DRAM. As shown in FIG. 1, write operations are performed in accordance with a rising edge of the clock signal, and one bit of data is written each clock cycle. Likewise, read operations are performed in accordance with the rising edge of the clock signal, and one bit of data is read each clock cycle.
In contrast, FIG. 2 is a timing diagram illustrating read write operations for a DDR DRAM. Referring to FIG. 2, write operations are performed in accordance with rising and falling edges of the clock signal, and two bits of data are written each clock cycle. Likewise, read operations are performed in accordance with rising and falling edges of the clock signal, and two bits of data are read each clock cycle.
As may be seen from FIGS. 1 and 2, the DDR DRAM has a data access speed twice that of the SDR DRAM. However, it is often difficult to double the operating speed of a memory cell array and a corresponding cell core in order to actually obtain the faster access speeds offered by the DDR DRAM design.
As a result, it is conventional to retain the SDR operating speed of the memory cell array, but provide twice as many data lines that operate in a data prefetch scheme. With the data prefetch scheme and twice the number of data lines, twice as much data may be transferred to an output buffer, as compared with operation of a SDR DRAM. Once prefetched data is stored in the buffer, it may be output on the rising edge and falling edges of the clock signal to provide DDR DRAM access rates without necessarily impacting the core operating rate of the memory cell array.
FIG. 3 illustrates a data output circuit for a conventional DDR DRAM. For purposes of clarity, two data path lines P1 and P2 corresponding to one input/output pad PD1 are illustrated in FIG. 3. A data sensing output unit 100 outputs first and second data DIOF and DIOS in parallel on first and second data path lines P1 and P2, respectively. First and second data DIOF and DIOS are sensed through input/output sense amplifiers. A constituent data transmitter 200 includes a plurality of transmission gates FG1, FG2, and FG3. Transmission gate FG1 operationally connects first data path line P1 with data output circuit 300 in response to a first control clock signal CLK_F generated by a system clock. Together, transmission gates FG2 and FG3 operationally connect second data path line P2 with data output circuit 300. Transmission gate FG2 is responsive to first control clock signal CLK_F, and transmission gate FG3 is responsive to second control clock signal CLK_S generated by the system clock. An associated data output circuit 300 having first and second level shifters 310 and 320 alternately (i.e., serially) outputs the data applied in parallel to first and second data path lines P1 and P2. Through the operation of the data output circuit of FIG. 3, input/output pad PD1 receives data serially in accordance with the rising and falling edges of a system clock signal CLK.
FIG. 4 is a timing diagram further illustrating the data output operations of the data output circuit shown in FIG. 3. Like reference symbols indicate like signals in FIGS. 3 and 4. A data output operation of the data output circuit of FIG. 3 will now be described with reference to FIGS. 3 and 4.
System clock signal CLK controls operation of the DRAM including the data output circuit illustrated in FIG. 3. Data sensing output unit 100 of FIG. 3 outputs first and second data DIOF and DIOS to first and second data path lines P1 and P2, respectively. First and second data DIOF and DIOS are each sensed and amplified through input/output sense amplifiers of data sensing output unit 100. First and second control clock signals CLK_F and CLK_S derived from the system clock signal are applied to data transmitter 200 having transmission gates FG1, FG2, and FG3.
After first and second data DIOF and DIOS are output to first and second data path lines P1 and P2, respectively, first data DIOF is provided to an input terminal of transmission gate FG1, and second data DIOS is provided to an input terminal of transmission gate FG2. After transmission gate FG1 receives first control clock signal CLK_F, first data DIOF is delayed by a time tD, as shown in FIG. 4, and then output on an output terminal of first transmission gate FG1 as a first data DIOF1. Likewise, after transmission gate FG2 receives first control clock signal CLK_F, second data DIOS is delayed by a time tD, as shown in FIG. 4, and then output on an output terminal of second transmission gate FG2 as a second data DIOS1. Transmission gates FG1 and FG2 each respond to first control clock signal CLK_F, so first data DIOF1 and second data DIOS1 are provided to the output terminals of transmission gates FG1 and FG2, respectively, at the same time.
Second data DIOS1 is then latched at the output terminal of second transmission gate FG2. Subsequently, in response to second control clock signal CLK_S, second data DIOS1 is output by transmission gate FG3 as second data DIOS2. First data DIOF is output through input/output pad PD1 synchronously with the rising edge of system clock signal CLK, and second data DIOS is output through input/output pad PD1 synchronously with the falling edge of system clock signal CLK.
As shown in the timing diagram of FIG. 4, first and second data DIOF and DIOS are output from data sensing output unit 100 at the same time. However, first and second data DIOF and DIOS are output through input/output pad PD1 (i.e., output from the chip having the data output circuit of FIG. 3) half a clock cycle apart. This temporal disparity between data signals does not impede satisfactory operation of the data output circuit so long as the second data DIOS is applied to second data path line P2 before the second control clock CLK_S is activated (i.e., during a time period T1). However, the conventional data output circuit of FIG. 3 has transmission gate FG2 that responds to first control clock signal CLK_F, and second data DIOS is latched between transmission gates FG2 and FG3 as second data DIOS1. Maintaining second data DIOS between transmission gates FG2 and FG3 of second data path line P2 consumes current in the conventional data output circuit of FIG. 3. In addition, in a semiconductor memory device in accordance with the conventional data output circuit of FIG. 3 and comprising multiple input/output pads, an element such as transmission gate FG2 will be present for every input/output pad of the device, and each transmission gate FG2 will contribute to the size and cost of the semiconductor memory device.
Thus, a smaller data output circuit that reduces unnecessary current consumption but does not decrease data output speed is required.